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Central processing units are the brains behind any computer system.This page provides an overview of the Pentium 1 based central processing unit.
 
Complete guide to Central Processing Units
Introductions Principles Of The CPU Evolution Of The CPU Overclocking
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Quick Specifications:
Processor Label: P5 586 Pentium # Of Transistors:

3.1 million (1st generation).
3.3 million (2nd generation).

Generation: 5th Generation Cache Memory: 8 KB Data, 8 KB Instruction
Release Year: Mar. 1993 - Jun. 1996 Memory Bus Speed: 60mhz - 66mhz
Data Bus Width: 64 bits Clock Speed Range: 60 / 66MHz (first generation); 75 / 90 / 100/ 120 / 133 / 150 / 166 / 200MHz 
Address Bus Width: 32 bits    
More Information:
Picture of this processor.

After the fourth-generation chips such as the 486, Intel and other chip manufacturers went back to the drawing board to come up with new architectures and features that they would later incorporate into what they called fifth-generation chips.

On October 19, 1992, Intel announced that the fifth generation of its compatible microprocessor line (code-named P5) would be named the Pentium processor. The actual Pentium chip shipped on March 22, 1993. Systems that used these chips were only a few months behind.

Pentium, like Celeron and Athlon, has become a brand name in recent years rather than identifying a particular processor type. This section discusses the original Pentium processors for Socket 5 and Socket 7.

The Pentium is fully compatible with previous Intel processors, but it differs from them in many ways. At least one of these differences is revolutionary: The Pentium features twin data pipelines, which enable it to execute two instructions at the same time. The 486 and all preceding chips can perform only a single instruction at a time. Intel calls the capability to execute two instructions at the same time superscalar technology. This technology provides additional performance compared to the 486.

With superscalar technology, the Pentium can execute many instructions at a rate of two instructions per cycle. Superscalar architecture usually is associated with high-output RISC chips. The Pentium is one of the first CISC chips to be considered superscalar. The Pentium is almost like having two 486 chips under the hood. Table 1.1  shows the Pentium processor specifications.

Table 1.1 - Pentium Processor Specifications
Introduced March 22, 1993 (first generation); March 7, 1994 (second generation)
Maximum rated speeds 60/66MHz (first generation); 75/90/100/120/133/150/166/200MHz (second generation)
CPU clock multiplier 1x (first generation); 1.5x–3x (second generation)
Register size 32-bit
External data bus 64-bit
Memory address bus 32-bit
Maximum memory 4GB
Integral-cache size 8KB code; 8KB data
Integral-cache type Two-way set associative; write-back data
Burst-mode transfers Yes
Number of transistors 3.1 million (first generation); 3.3 million (second generation)
Circuit size 0.8 micron (60/66MHz); 0.6 micron (75MHz-100MHz); 0.35 micron (120MHz and up)
External package 273-pin PGA; 296-pin SPGA; tape carrier
Math coprocessor Built-in FPU
Power management SMM; enhanced in second generation
Operating voltage 5V (first generation); 3.465V, 3.3V, 3.1V, 2.9V (second generation)
PGA = Pin grid array
SPGA = Staggered pin grid array

The two instruction pipelines within the chip are called the u- and v-pipes. The u-pipe, which is the primary pipe, can execute all integer and floating-point instructions. The v-pipe is a secondary pipe that can execute only simple integer instructions and certain floating-point instructions. The process of operating on two instructions simultaneously in the different pipes is called pairing. Not all sequentially executing instructions can be paired, and when pairing is not possible, only the u-pipe is used. To optimize the Pentium’s efficiency, you can recompile software to enable more instructions to be paired.

The Pentium processor has a branch target buffer (BTB), which employs a technique calledbranch prediction. It minimizes stalls in one or more of the pipes caused by delays in fetching instructions that branch to nonlinear memory locations. The BTB attempts to predict whether a program branch will be taken and then fetches the appropriate instructions. The use of branch prediction enables the Pentium to keep both pipelines operating at full speed. Figure 1.2 shows the internal architecture of the Pentium processor.

Figure 1.2 - Pentium processor internal architecture.

The Pentium has a 32-bit address bus width, giving it the same 4GB memory-addressing capabilities as the 386DX and 486 processors. But the Pentium expands the data bus to 64 bits, which means it can move twice as much data into or out of the CPU, compared to a 486 of the same clock speed. The 64-bit data bus requires that system memory be accessed 64 bits wide, so each bank of memory is 64 bits.

Even though the Pentium has a 64-bit data bus that transfers information 64 bits at a time into and out of the processor, the Pentium has only 32-bit internal registers. As instructions are being processed internally, they are broken down into 32-bit instructions and data elements and processed in much the same way as in the 486. Some people thought that Intel was misleading them by calling the Pentium a 64-bit processor, but 64-bit transfers do indeed take place. Internally, however, the Pentium has 32-bit registers that are fully compatible with the 486.

The Pentium, like the 486, contains an internal math coprocessor or FPU. The FPU in the Pentium was rewritten to perform significantly better than the FPU in the 486 yet still be fully compatible with the 486 and 387 math coprocessors. The Pentium FPU is estimated to be two to as much as ten times faster than the FPU in the 486. In addition, the two standard instruction pipelines in the Pentium provide two units to handle standard integer math. (The math coprocessor handles only more complex calculations.) Other processors, such as the 486, have only a single standard execution pipe and one integer math unit.

To learn more about Pentium processors, including the famous floating-point calculation flaw, see Chapter 3 of Upgrading and Repairing PCs, 19th edition, available in its entirety on the disc packaged with this book.

AMD-K5

The AMD-K5 is a Pentium-compatible processor developed by AMD and available as the PR75, PR90, PR100, PR120, PR133, PR166, and PR200. Because it is designed to be physically and functionally compatible, any motherboard that properly supports the Intel Pentium should support the AMD-K5. However, a BIOS upgrade might be required to properly recognize the AMD-K5. The K5 has the following features:

  • 16KB instruction cache, 8KB write-back data cache

  • Dynamic execution-branch prediction with speculative execution

  • Five-stage, RISC-like pipeline with six parallel functional units

  • High-performance floating-point unit

  • Pin-selectable clock multiples of 1.5x, 1.75x, and 2x

 

 
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