The ingot is then ground into a perfect 200mm- (8-inch) or 300mm-diameter (12-inch) cylinder, with a small flat or notch cut on one side for handling and positioning. Each ingot is then sliced with a high-precision saw into more than a thousand circular wafers, each less than a millimeter thick. The wafers are then polished to a mirror-smooth surface to make them ready for imprinting. A finished wafer with imprinted chips is shown in Figure 3.5.
Figure 3.5. 200mm (8-inch) wafer containing 177 full Pentium 4 Northwood (0.13-micron) processor cores.
Chips are manufactured from the wafers using a process called photolithography. Through this photographic process, transistors and circuit and signal pathways are created in semiconductors by depositing different layers of various materials on the chip, one after the other. Where two specific circuits intersect, a transistor or switch can form.
The photolithographic process starts when an insulating layer of silicon dioxide is grown on the wafer through a vapor deposition process. Then a coating of photoresist material is applied, and an image of that layer of the chip is projected through a mask onto the now light-sensitive surface.
Doping is the term that describes chemical impurities added to silicon (which is naturally a nonconductor), creating a material with semiconductor properties. The projector uses a specially created mask, which is essentially a negative of that layer of the chip etched in chrome on a quartz plate. Modern processors have 20 or more layers of material deposited and partially etched away (each requiring a mask) and up to six or more layers of metal interconnects.
As the light passes through a mask, the light is focused on the wafer surface, exposing the photoresist with the image of that layer of the chip. Each individual chip image is called a die. A device called a stepper then moves the wafer over a little bit, and the same mask imprints another chip die immediately next to the previous one. After the entire wafer is imprinted with a layer of material and photoresist, a caustic solution washes away the areas where the light struck the photoresist, leaving the mask imprints of the individual chip circuit elements and pathways. Then another layer of semiconductor material is deposited on the wafer with more photoresist on top, and the next mask exposes and then etches the next layer of circuitry. Using this method, the layers and components of each chip are built one on top of the other until the chips are completed (refer to Figure 3.5).
Some of the masks add the metallization layers, which are the metal interconnects that tie all the individual transistors and other components together. Most older chips use aluminum interconnects, although in 2002 many moved to copper. The first commercial PC processor chip to use copper was the 0.18-micron Athlon made in AMD’s Dresden fab, and Intel shifted the Pentium 4 to copper with the 0.13-micron Northwood version. Copper is a better conductor than aluminum and allows smaller interconnects with less resistance, meaning smaller and faster chips can be made. Copper hadn’t been used previously because there were difficult corrosion problems to overcome during the manufacturing process that were not as much of a problem with aluminum.
Another technology used in chip manufacturing is called silicon on insulator (SOI). SOI uses a layered silicon-insulator-silicon wafer substrate to reduce parasitic device capacitance, thus reducing current leakage and improving performance. In particular, AMD has used SOI for many of its processors since 2001.
A completed circular wafer has as many chips imprinted on it as can possibly fit. Because each chip usually is square or rectangular, there are some unused portions at the edges of the wafer, but every attempt is made to use every square millimeter of surface.
The industry is going through several transitions in chip manufacturing. The trend in the industry is to use both larger wafers and a smaller manufacturing process. The process refers to the size and line spacing of the individual circuits and transistors on the chip, whereas the wafer size refers to the diameter of the circular wafers on which the chips are imprinted.
In 2002, chip manufacturing began moving from 200mm (8-inch) diameter wafers to larger 300mm (12-inch) wafers. The larger 300mm wafers enable more than double the number of chips to be made compared to the 200mm used previously. In addition, the transitions to smaller and smaller processes enable more transistors to be incorporated into the chip die.
With more recent processors, smaller manufacturing processes have also been used to make more space available in each processor die for features such as multiple processor cores, CPU-integrated video, and large L3 caches. Thus, the Nehalem Core i7 six-core processor, although it uses a 45nm process, has a much larger core size than the Pentium 4 Northwood (which was built on a 130nm process): 263 square millimeters for the Nehalem (731 million transistors), versus just 131 square millimeters for Northwood (55 million transistors). As a result, the Nehalem Core i7 processors have a yield of 240 die candidates per wafer, about half of the yield of the Northwood.
The industry began moving to the 90-nanometer (0.09-micron) process in 2004, the 65-nanometer in 2006, the 45-nanometer process in 2008, and the 32-nanometer process in 2010.
These will still be made on 300mm wafers because the next wafer transition isn’t expected until 2014, when a transition to 450mm wafers is expected.
CPU Manufacturing Process and Silicon Wafer Size
Table 3.8 shows the CPU manufacturing process and silicon wafer size transitions for the first 30 years from when the processor debuted (1971–2001).Table 3.9 shows the continuing evolution of these transitions from 2002 through the present, and all the way to 2022, including several planned future transitions.
Table 3.8. CPU Process/Wafer Size Transitions from 1971 to 2001
|Mfg. Process (microns)
|Mfg. Process (nanometers)
|Wafer Size (millimeters)
|Wafer Size (inches)
|Intel first used 150mm (6 inch) wafers in 1983 and 200mm (8 inch) wafers in 1993.
Table 3.9. CPU Process/Wafer Size Transitions from 2002 to 2022
|Mfg. Process (microns)
|Mfg. Process (nanometers)
|Wafer Size (millimeters)
|Wafer Size (inches)
|Intel first used 300mm (12-inch) wafers in 2002.
Note that not all the chips on each wafer will be good, especially as a new production line starts. As the manufacturing process for a given chip or production line is perfected, more and more of the chips will be good. The ratio of good to bad chips on a wafer is called the yield. Yields well below 50% are common when a new chip starts production; however, by the end of a given chip’s life, the yields are normally in the 90% range. Most chip manufacturers guard their yield figures and are secretive about them because knowledge of yield problems can give their competitors an edge. A low yield causes problems both in the cost per chip and in delivery delays to their customers. If a company has specific knowledge of competitors’ improving yields, it can set prices or schedule production to get higher market share at a critical point.
After a wafer is complete, a special fixture tests each of the chips on the wafer and marks the bad ones to be separated later. The chips are then cut from the wafer using either a high-powered laser or a diamond saw.
After being cut from the wafers, the individual dies are retested, packaged, and retested again. The packaging process is also referred to as bondingbecause the die is placed into a chip housing in which a special machine bonds fine gold wires between the die and the pins on the chip. The package is the container for the chip die, which essentially seals it from the environment.
After the chips are bonded and packaged, final testing is done to determine both proper function and rated speed. Different chips in the same batch often run at different speeds. Special test fixtures run each chip at different pressures, temperatures, and speeds, looking for the point at which the chip stops working. At this point, the maximum successful speed is noted and the final chips are sorted into bins with those that tested at a similar speed.
One interesting thing about this is that as a manufacturer gains more experience and perfects a particular chip assembly line, the yield of the higher-speed versions goes way up. So, of all the chips produced from a single wafer, perhaps more than 75% of them check out at the highest speed, and only 25% or less run at the lower speeds. The paradox is that Intel often sells a lot more of the lower-priced, lower-speed chips, so it just dips into the bin of faster ones, labels them as slower chips, and sells them that way. People began discovering that many of the lower-rated chips actually ran at speeds much higher than they were rated, and the business of overclocking was born. Similarly, some lower-cost multi-core processors from AMD have the same physical number of cores as higher-cost ones, but some cores are disabled during manufacturing.
Processor remarking, the alterations of chip marking to make a slower chip masquerade as a faster chip, was once a major problem when virtually all processors could be overclocked (run at faster clock speeds than normal). However, with the advent of retail boxed processors, clock multiplier locks in most models, and utility programs such as CPU-Z that can identify processor names and features, processor remarking is now minimal compared to its heyday over a decade ago.
To make sure your system has the processor you paid for, download and run a copy of CPU-Z (http://www.cpuid.com/softwares/cpu-z.html). CPU-Z is the de facto standard for CPU identification and feature display.
PGA Chip Packaging
Variations on the pin grid array (PGA) chip packaging have been the most commonly used chip packages over the years. They were used starting with the 286 processor in the 1980s and are still used today, although not in all CPU designs. PGA takes its name from the fact that the chip has a grid-like array of pins on the bottom of the package. PGA chips are inserted into sockets, which are often of a zero insertion force (ZIF) design. A ZIF socket has a lever to allow for easy installation and removal of the chip.
Most original Pentium processors use a variation on the regular PGA called staggered pin grid array (SPGA), in which the pins are staggered on the underside of the chip rather than in standard rows and columns. This was done to move the pins closer together and decrease the overall size of the chip when a large number of pins is required. Figure 3.6 shows a Pentium Pro that uses the dual-pattern SPGA (on the right) next to a Pentium 66 that uses the regular PGA. Note that the right half of the Pentium Pro shown here has additional pins staggered among the other rows and columns.
Figure 3.6. PGA on Pentium 66 (left) and dual-pattern SPGA on Pentium Pro (right).
Early PGA variations mounted the processor die in a cavity under the substrate, whereas so-called “Flip Chip” versions mount the processor die upside down so that less expensive solder bonding rather than expensive wire bonding can be used to connect the processor die to the chip package.
Unfortunately, there were some problems with attaching the heatsink to an FC-PGA chip. The heatsink sat on the top of the die, which acted as a pedestal. If you pressed down on one side of the heatsink excessively during the installation process (such as when you were attaching the clip), you risked cracking the silicon die and destroying the chip. This was especially a problem as heatsinks became larger and heavier and the force applied by the clip became greater. Intel and AMD now use a metal cap called a heat spreader over the top of the CPU to prevent damage when the heatsink is installed. This type of packaging is known as FC-PGA2 and was used by Intel for all Pentium 4 and subsequent chips. AMD began to use it with its Athlon 64 processors and subsequent chips.
Future packaging directions may include what is called bumpless build-up layer (BBUL) packaging. This embeds the die completely in the package; in fact, the package layers are built up around and on top of the die, fully encapsulating it within the package. This embeds the chip die and allows for a full flat surface for attaching the heatsink, as well as shorter internal interconnections within the package. BBUL is designed to handle extremely high clock speeds of 20GHz or faster, but is not yet necessary.
Single Edge Contact and Single Edge Processor Packaging
Intel and AMD used cartridge- or board-based packaging for some of their processors from 1997 through 2000. This packaging was called single edge contact cartridge (SECC) or single edge processor package (SEPP) and consisted of the CPU and optional separate L2 cache chips mounted on a circuit board that looked similar to an oversized memory module and that plugged into a slot. In some cases, the boards were covered with a plastic cartridge.